STN EN 16603-20-40
| Name: | STN EN 16603-20-40 |
| Validity: | Valid |
| Number of pages: | 140 |
| Language: |
EN
|
| Paper: | 36,30€ |
| Electronic version |
a) Only read (without ability to print and copy)
32,67€ b) Without ability to print, with ability to copy (printscreen) 36,30€ c) With ability to print and copy (printscreen) 47,19€ |
| Slovak title | Kozmická technika. Inžinierstvo ASIC, FPGA a IP Core |
| English title | Space engineering - ASIC, FPGA and IP Core engineering |
| Release Date: | 01. 04. 2024 |
| Date of withdrawal: | |
| ICS: | 49.140 |
| Sorting character/National clasification code | 31 0543 |
| Level of incorporation: | idt EN 16603-20-40:2023 |
| Official Journal | 03/24 |
| Amendments | |
| Replaced by: | |
| Repleces: | |
| Note in Official Journal: | |
| Subject of the standard: | This activity w ill be the parallel development of EN 16603-20-40 and ECSS-E-ST-20-40C. The scope shall cover the areas of existing ASIC and FPGA engineering chapter 5 of ECSS-Q-ST-60-02C, but w ith w ider breadth and greater depth, covering engineering requirements of end-to-end development flow s, from specification of requirements to validation of prototypes, of the follow ing monolithic devices for its use in space: • ASICs (distinguishing digital, analogue and mixed-signal development flow s) • FPGAs (distinguishing three technology families: SRAM, FLASH and anti-fuse technologies) • ASIC and FPGA System-on-Chip embedding processor cores w hich have external “softw are programme” dependencies to be addressed during the SoC development, resulting in SW-HW co-design requirements. |
| Preview: | Náhľad normy (PDF) |