STN EN 16603-20-40
| Označenie: | STN EN 16603-20-40 |
| Platnosť: | Platná |
| Počet strán: | 140 |
| Jazyk: |
EN
|
| Listinná verzia: | 36,30€ |
| Elektronická verzia: |
a) Bez možnosti tlače, prenosu textu a obrázkov:
32,67€ b) Bez možnosti tlače, s prenosom textu a obrázkov: 36,30€ c) S možnosťou tlače, prenosu textu a obrázkov: 47,19€ |
| Slovenský názov: | Kozmická technika. Inžinierstvo ASIC, FPGA a IP Core |
| Anglický názov: | Space engineering - ASIC, FPGA and IP Core engineering |
| Dátum vydania: | 01. 04. 2024 |
| Dátum zrušenia: | |
| ICS: | 49.140 |
| Triediaci znak: | 31 0543 |
| Úroveň zapracovania: | idt EN 16603-20-40:2023 |
| Vestník: | 03/24 |
| Zmeny: | |
| Nahradzujúce normy: | |
| Nahradené normy: | |
| Poznámka vo Vestníku: | |
| Predmet normy: | This activity w ill be the parallel development of EN 16603-20-40 and ECSS-E-ST-20-40C. The scope shall cover the areas of existing ASIC and FPGA engineering chapter 5 of ECSS-Q-ST-60-02C, but w ith w ider breadth and greater depth, covering engineering requirements of end-to-end development flow s, from specification of requirements to validation of prototypes, of the follow ing monolithic devices for its use in space: • ASICs (distinguishing digital, analogue and mixed-signal development flow s) • FPGAs (distinguishing three technology families: SRAM, FLASH and anti-fuse technologies) • ASIC and FPGA System-on-Chip embedding processor cores w hich have external “softw are programme” dependencies to be addressed during the SoC development, resulting in SW-HW co-design requirements. |
| Náhľad normy: | Náhľad normy (PDF) |